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19-1579; Rev 5; 8/10
10-Bit, 40MHz, Current/Voltage-Output DACs
General Description
The MAX5181 is a 10-bit, current-output digital-to-analog converter (DAC) designed for superior performance in signal reconstruction or arbitrary waveform generation applications requiring analog signal reconstruction with low distortion and low-power operation. The MAX5184 provides equal specifications, with on-chip precision resistors for voltage-output operation. The MAX5181/MAX5184 are designed for a 10pVs glitch operation to minimize unwanted spurious signal components at the output. An on-board 1.2V bandgap circuit provides a well-regulated, low-noise reference that can be disabled for external reference operation. The devices are designed to provide a high level of signal integrity for the least amount of power dissipation. They operate from a single 2.7V to 3.3V supply. Additionally, these DACs have three modes of operation: normal, low-power standby, and full shutdown, which provides the lowest possible power dissipation with a 1A (max) shutdown current. A fast wake-up time (0.5s) from standby mode to full DAC operation facilitates power conservation by activating the DAC only when required. The MAX5181/MAX5184 are available in 24-pin QSOP packages and are specified for the extended (-40C to +85C) temperature range. Additionally, the MAX5184 is also available in a 24-pin TQFN with exposed pad (EP) and is specified for the extended (-40C to +85C) temperature range. For lower resolution, 8-bit versions, refer to the MAX5187/MAX5190 data sheet.
Features
o 2.7V to 3.3V Single-Supply Operation o Wide Spurious-Free Dynamic Range: 70dB at fOUT = 2.2MHz o Fully Differential Output o Low-Current Standby or Full Shutdown Modes o Internal 1.2V, Low-Noise Bandgap Reference o Small 24-Pin QSOP and Thin QFN Packages
MAX5181/MAX5184
Ordering Information
PART MAX5181BEEG+ MAX5184BEEG+ MAX5184ETG+ MAX5184ETG/V+ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 24 QSOP 24 QSOP 24 TQFN-EP* 24 TQFN-EP*
*EP = Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configurations
TOP VIEW
CREF 1 OUTP 2 OUTN 3 AGND 4 AVDD 5 DACEN 6 PD 7 CS 8 CLK 9 REN 10 D0 11 D1 12
Applications
Signal Reconstruction Arbitrary Waveform Generators (AWGs) Direct Digital Synthesis Imaging Applications
+
24 REFO 23 REFR 22 DGND 21 DVDD
MAX5181 MAX5184
20 D9 19 D8 18 D7 17 D6 16 D5 15 D4 14 D3 13 D2
QSOP
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD to AGND, DGND .................................-0.3V to +6V Digital Inputs to DGND.............................................-0.3V to +6V OUTP, OUTN, CREF to AGND .................................-0.3V to +6V VREF to AGND ..........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AVDD to DVDD .................................................................... 3.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 24-Pin QSOP (derate 9.50mW/C above +70C) ........762mW 24-Pin TQFN (derate 20.8mW/C above +70C) ............................1667mW Operating Temperature Range MAX518_BEEG ................................................-40C to +85C MAX5184ETG ..................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = 3V, VAGND = VDGND = 0V, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Zero-Scale Error Full-Scale Error DYNAMIC PERFORMANCE Output Settling Time Glitch Impulse Spurious-Free Dynamic Range to Nyquist fCLK = 40MHz, fOUT = 500kHz SFDR fCLK = 40MHz, fOUT = 2.2MHz, TA = +25C fCLK = 40MHz, fOUT = 500kHz MAX518_BEEG Total Harmonic Distortion to Nyquist THD MAX5184ETG fCLK = 40MHz, fOUT = 2.2MHz, TA = +25C fCLK = 40MHz, fOUT = 2.2MHz, TA = +25C fCLK = 40MHz, fOUT = 500kHz Signal-to-Noise Ratio to Nyquist Clock and Data Feedthrough Output Noise ANALOG OUTPUT Full-Scale Output Voltage Voltage Compliance of Output Output Leakage Current DACEN = 0, MAX5181 only VFS -0.3 -1 400 0.8 1 mV V A SNR MAX518_BEEG MAX5184ETG All 0s to all 1s fCLK = 40MHz, fOUT = 2.2MHz, TA = +25C fCLK = 40MHz, fOUT = 2.2MHz 56 57 To 0.5LSB error band 25 10 72 70 -70 -68 -68 61 59 59 50 10 nVs pA/Hz dB -63 -57 dBc dBc ns pVs N INL DNL Guaranteed monotonic MAX5181 MAX5184 (Note 1) 10 -2 -1 -2 -8 -40 15 0.5 0.5 +2 1 +2 +8 +40 Bits LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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10-Bit, 40MHz, Current/Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 3V, VAGND = VDGND = 0V, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Full-Scale Output Current DAC External Output Resistor load REFERENCE Output Voltage Range Output Voltage Temperature Drift Reference Output Drive Capability Reference Supply Rejection Current Gain (IFS / IREF) POWER REQUIREMENTS Analog Power-Supply Voltage Analog Supply Current Digital Power-Supply Voltage Digital Supply Current Standby Current Shutdown Current LOGIC INPUTS AND OUTPUTS Digital Input Voltage High Digital Input Voltage Low Digital Input Current Digital Input Capacitance TIMING CHARACTERISTICS DAC DATA to CLK Rise Setup Time DAC CLK Rise to DATA Hold Time CS Fall to CLK Rise Time CS Fall to CLK Fall Time DACEN Rise Time to VOUT PD Fall Time to VOUT Clock Period Clock High Time Clock Low Time tCLK tCH tCL 25 10 10 tDS tDH 10 0 5 5 0.5 50 ns ns ns ns s s ns ns ns VIH VIL IIN CIN VIN = 0V or DVDD 10 2 0.8 1 V V A pF AVDD IAVDD DVDD IDVDD ISTANDBY ISHDN PD = 0, DACEN = 1, digital inputs at 0V or DVDD PD = 0, DACEN = 0, digital inputs at 0V or DVDD PD = 1, DACEN = X,digital inputs at 0V or DVDD (X = don't care) PD = 0, DACEN = 1, digital inputs at 0V or DVDD 2.7 4.2 1.0 0.5 2.7 1.7 3.3 4.0 3.3 5.0 1.5 1 V mA V mA mA A VREF TCVREF IREFOUT 1.12 1.2 50 10 0.5 8 1.28 V ppm/C A mV/V mA/mA SYMBOL IFS RL MAX5181 only MAX5181 only CONDITIONS MIN 0.5 TYP 1 400 MAX 1.5 UNITS mA
MAX5181/MAX5184
Note 1: Excludes reference and reference resistor (MAX5184) tolerance.
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10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
Typical Operating Characteristics
(AVDD = DVDD = 3V, VAGND = VDGND = 0V, IFS = 1mA, 400 differential output, CL = 5pF, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. INPUT CODE
MAX5181/4toc01
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
MAX5181/4toc02
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5181/4toc03
0.6 0.5 0.4
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3
3.0 ANALOG SUPPLY CURRENT (mA)
2.5
0.3 INL (LSB) 0.2 0.1 0 -0.1 -0.2 0 128 256 384 512 640 768 896 1024 INPUT CODE
2.0 MAX5184 1.5 MAX5181
1.0 0 128 256 384 512 640 768 896 1024 INPUT CODE 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5181/4toc04
DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5181/4toc05
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX5181/4toc06
3.0 ANALOG SUPPLY CURRENT (mA)
8 DIGITAL SUPPLY CURRENT (mA)
4.00 DIGITAL SUPPLY CURRENT (mA)
2.5
7 MAX5184 6 MAX5181 5 4
3.75 MAX5184 3.50 MAX5181 3.25
2.0 MAX5184 1.5 MAX5181
1.0 -40 -15 10 35 60 85 TEMPERATURE (C)
3 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
3.00 -40 -15 10 35 60 85 TEMPERATURE (C)
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX5181/4toc07
STANDBY CURRENT vs. TEMPERATURE
MAX5181/4toc08
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
MAX5181/4toc09
610
600
0.14
STANDBY CURRENT (A)
MAX5184
STANDBY CURRENT (A)
600
580 MAX5181 570
SHUTDOWN CURRENT (A)
590
MAX5184
0.12
0.10 MAX5181 0.08
590 MAX5181 580
560
0.06
MAX5184
570 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
550 -40 -15 10 35 60 85 TEMPERATURE (C)
0.04 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
4
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10-Bit, 40MHz, Current/Voltage-Output DACs
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, VAGND = VDGND = 0V, IFS = 1mA, 400 differential output, CL = 5pF, TA = +25C, unless otherwise noted.)
MAX5181/MAX5184
SHUTDOWN CURRENT vs. TEMPERATURE
MAX5181/4toc10
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX5181/4toc11
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX5181/4toc12
0.13
1.28
1.28
SHUTDOWN CURRENT (A)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
0.11
1.27
1.27
0.09
MAX5181
1.26 MAX5184 1.25 MAX5181
1.26 MAX5181 1.25 MAX5184
0.07 MAX5184 0.05
1.24
1.24
0.03 -40 -15 10 35 60 85 TEMPERATURE (C)
1.23 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
1.23 -40 -15 10 35 60 85 TEMPERATURE (C)
OUTPUT CURRENT vs. REFERENCE CURRENT
MAX5181/4toc13
DYNAMIC RESPONSE RISE TIME
MAX5181/4toc14
DYNAMIC RESPONSE FALL TIME
MAX5181/4toc15
4
OUTPUT CURRENT (mA)
3
OUTP 150mV/ div
OUTP 150mV/ div
2
1
OUTN 150mV/ div
OUTN 150mV/ div
0 0 100 200 300 400 500 500ns/div 500ns/div REFERENCE CURRENT (A)
SETTLING TIME
MAX5181/4toc16
FFT PLOT
MAX5181/4toc17
SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY
fOUT = 2.2MHz fCLK = 40MHz
MAX5181/4toc18
0 -10 -20 -30 OUTN 100mV/ div -40 -50 -60 -70 -80 OUTP 100mV/ div -90 -100 -110 -120 0 2 4 6 8
100 90 80 SFDR (dBc) 70 60 50 40
(dBc)
12.5ns/div
10 12 14 16 18 20
10 15 20 25 30 35
40 45
50 55 60
OUTPUT FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
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10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, VAGND = VDGND = 0V, IFS = 1mA, 400 differential output, CL = 5pF, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY AND CLOCK FREQUENCY
fCLK = 40MHz 76 74 SFDR (dBc) 72 70 61.2 68 fCLK = 30MHz 66 500 900 1300 1700 2100 OUTPUT FREQUENCY (kHz) 60.8 0 500 1000 1500 2000 2500 OUPUT FREQUENCY (kHz) 61.0 fCLK = 20MHz fCLK = 50MHz
MAX5181/4toc19
SIGNAL-TO-NOISE PLUS DISTORTION vs. OUTPUT FREQUENCY
62.2 62.0 SIINAD (dB) 61.8 61.6 61.4
MAX5181/4toc20
78
62.4
fCLK = 10MHz
fCLK = 60MHz
MULTITONE SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY
MAX5181/4toc21
SPURIOUS-FREE DYNAMIC RANGE vs. FULL-SCALE OUTPUT CURRENT
MAX5181/84-22
20 0 -20 SFDR (dBc)
74 72 70 SFDR (dBc) 68 66 64 62 60
-40 -60 -80 -100 -120 -140 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz)
0.5
0.75
1.0
1.25
1.5
FULL-SCALE OUTPUT CURRENT (mA)
6
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10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
Pin Description
PIN QSOP 1 2 3 4 5 TQFN 22 23 24 1 2 NAME CREF OUTP OUTN AGND AVDD REFO Positive Analog Output. Current output for MAX5181; voltage output for MAX5184. Negative Analog Output. Current output for MAX5181; voltage output for MAX5184. Analog Ground Analog Positive Supply, 2.7V to 3.3V DAC Enable, Digital Input 0: Enter DAC standby mode with PD = DGND 1: Power-up DAC with PD = DGND X: Enter shutdown mode with PD = DVDD (X = don't care) Power-Down Select 0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD) 1: Enter shutdown mode Active-Low Chip Select Clock Input Active-Low Reference Enable. Connect to DGND to activate on-chip 1.2V reference. Data Bit D0 (LSB) Data Bits D1-D8 Data Bit D9 (MSB) Digital Supply, 2.7V to 3.3V Digital Ground Reference Input Reference Output Exposed Pad (TQFN Only). Internally connected to AGND. Connected to the analog ground plane (AGND). FUNCTION
6
3
DACEN
7 8 9 10 11 12-19 20 21 22 23 24 --
4 5 6 7 8 9-16 17 18 19 20 21 --
PD CS CLK REN D0 D1-D8 D9 DVDD DGND REFR REFO EP
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7
10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
Detailed Description
The MAX5181/MAX5184 are 10-bit digital-to-analog converters (DACs) capable of operating with clock speeds up to 40MHz. Each converter consists of separate input and DAC registers, followed by a current source array capable of generating up to 1.5mA full-scale output current (Figure 1). An integrated 1.2V voltage reference and control amplifier determine the data converters' full-scale output currents/voltages. Careful reference design ensures close gain matching and excellent drift characteristics. The MAX5184's voltage output operation features matched 400 on-chip resistors that convert the current-array current into a voltage. provides a 1.2V output. Due to its limited 10A output drive capability, REFO must be buffered with an external amplifier, if heavier loading is required. The MAX5181/MAX5184 also employ a control amplifier designed to regulate simultaneously the full-scale output current (IFS) for both outputs of the devices. The output current is calculated as follows: IFS = 8 IREF where I REF is the reference output current (I REF = VREFO/RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the amplifier's output current on the MAX5181 (Figure 2). This current is mirrored into the current source array, where it is equally distributed between matched current segments and summed to valid output current readings for the DACs. The MAX5184 converts this output current into a differential output voltage (VOUT) with two internal, groundreferenced 400 load resistors. Using the internal 1.2V reference voltage, the MAX5184's integrated
Internal Reference and Control Amplifier
The MAX5181/MAX5184 provide an integrated 50ppm/C, 1.2V, low-noise bandgap reference that can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to DGND, the internal reference is selected and REFO
REN 1.2V REF
AVDD
AGND
CS
DACEN
PD
REFO CURRENTSOURCE ARRAY REFR OUTP DAC SWITCHES 9.6k* OUTPUT LATCHES MSB DECODE CLK INPUT LATCHES OUTPUT LATCHES MSB DECODE INPUT LATCHES OUTN CREF
400*
400*
MAX5181 MAX5184
DVDD DGND
*INTERNAL 400 AND 9.6k RESISTORS FOR MAX5184 ONLY.
D9-D0
Figure 1. Functional Diagram
8 _______________________________________________________________________________________
10-Bit, 40MHz, Current/Voltage-Output DACs
reference output-current resistor (RSET = 9.6k) sets IREF to 125A and IFS to 1mA. supply current is reduced to 1A. To enter this mode, connect PD to DVDD. To return to active mode, connect PD to DGND and DACEN to DV DD. About 50s are required for the parts to leave shutdown mode and settle to their outputs' values prior to shutdown. Table 1 lists the power-down mode selection.
MAX5181/MAX5184
External Reference
To disable the MAX5181/MAX5184's internal reference, connect REN to DVDD. A temperature-stable, external reference may now be applied to drive the REFO pin to set the full-scale output (Figure 3). Choose a reference capable of supplying at least 150A to drive the bias circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a fixed output voltage reference such as the 1.2V, 25ppm/C MAX6520 bandgap reference.
Timing Information
Figure 4 shows a detailed timing diagram for the MAX5181/MAX5184. With each high transition of the clock, the input latch is loaded with the digital value set by bits D9 through D0. The content of the input latch is then shifted to the DAC register, and the output updates at the rising edge of the next clock.
Standby Mode
To enter the lower-power standby mode, connect digital inputs PD and DACEN to DGND. In standby, both the reference and the control amplifier are active with the current array inactive. To exit this condition, DACEN must be pulled high with PD held at DGND. The MAX5181/MAX5184 typically require 50s to wake up and let both outputs and the reference settle.
Outputs
The MAX5181 output is designed to supply full-scale output currents of 1mA into 400 loads in parallel with a capacitive load of 5pF. The MAX5184 features integrated 400 resistors that restore the array current to proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a single-ended voltage.
Shutdown Mode
For lowest power consumption, the MAX5181/MAX5184 provide a power-down mode in which the reference, control amplifier, and current array are inactive and the DAC
OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS REN MAX4040 1.2V BANDGAP REFERENCE REFO RSET CCOMP* AGND REFR IREF
DGND
CURRENTSOURCE ARRAY
IFS
RSET
RSET** 9.6k
AGND
MAX5181 MAX5184
*COMPENSATION CAPACITOR (CCOMP = 100nF)
**9.6k REFERENCE CURRENT-SET RESISTOR INTERNAL TO MAX5184 ONLY. USE EXTERNAL RSET FOR MAX5181.
Figure 2. Setting IFS with the Internal 1.2V Reference and the Control Amplifier
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10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
Table 1. Power-Down Mode Selection
PD (POWER-DOWN SELECT) 0 0 1 DACEN (DAC ENABLE) 0 1 X POWER-DOWN MODE Standby Wake-Up Shutdown OUTPUT STATE MAX5181 MAX5184 High-Z AGND
Last state prior to standby mode MAX5181 MAX5184 High-Z AGND
X = Don't care.
DVDD 10F REN 1.2V BANDGAP REFERENCE REFO CURRENTSOURCE ARRAY IFS DGND 0.1F
AVDD
EXTERNAL 1.2V REFERENCE
REFR
MAX6520
AGND RSET AGND 9.6k*
MAX5181 MAX5184
*9.6k REFERENCE CURRENT-SET RESISTOR INTERNAL TO MAX5184 ONLY. USE EXTERNAL RSET FOR MAX5181.
Figure 3. MAX5181/MAX5184 with External Reference
Applications Information
Static and Dynamic Performance Definitions
Integral Nonlinearity Integral nonlinearity (INL) (Figure 5a) is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function once offset and gain errors have
10
been nullified. For a DAC, the deviations are measured every single step.
Differential Nonlinearity Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
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10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
tCLK
tCL
tCH
CLK
D0-D9 tDS
N-1
N tDH
N+1
OUT
N-1
N
N+1
Figure 4. Timing Diagram
Offset Error Offset error (Figure 5c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated by trimming. Gain Error Gain error (Figure 5d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time Settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy. Digital Feedthrough Digital feedthrough is the noise generated on a DAC's output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal's first four harmonics to the fundamental itself. This is expressed as:
(V22 + V32 + V4 2 + V52 ) THD = 20 x log V1
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth amplifier may be used to generate a voltage from the array current output of the MAX5181. The differential voltage across OUTP and OUTN is converted into a single-ended voltage by designing an appropriate operational amplifier configuration (Figure 6).
I/Q Reconstruction in a QAM Application
The low-distortion performance of two MAX5181/ MAX5184s supports analog reconstruction of in-phase (I) and quadrature (Q) carrier components typically used in quadrature amplitude modulation (QAM) architectures where two separate buses carry the I and Q data. A QAM signal is both amplitude (AM) and phase modulated, created by summing two independently modulated carriers of identical frequency but different phase (90 phase difference). In a typical QAM application (Figure 7), the modulation occurs in the digital domain, and two DACs such as the MAX5181/MAX5184 may be used to reconstruct the analog I and Q components.
11
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10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
7 6 ANALOG OUTPUT VALUE 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (1/4 LSB ) AT STEP 011 (1/2 LSB ) ANALOG OUTPUT VALUE 5 4 3 1 LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+1/4 LSB) 1 LSB DIFFERENTIAL LINEARITY ERROR (-1/4 LSB)
6
Figure 5a. Integral Nonlinearity
Figure 5b. Differential Nonlinearity
3 ANALOG OUTPUT VALUE
ACTUAL DIAGRAM ANALOG OUTPUT VALUE
7
IDEAL FULL-SCALE OUTPUT GAIN ERROR (-1 1/4 LSB)
6 IDEAL DIAGRAM 5 ACTUAL FULL-SCALE OUTPUT
2 IDEAL DIAGRAM 1 ACTUAL OFFSET POINT IDEAL OFFSET POINT 000 001
OFFSET ERROR (+1 1/4 LSB)
4 0
0
010
011
000 100
101
110
111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 5c. Offset Error
Figure 5d. Gain Error
The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed components with in-phase and quadrature carrier frequencies and then sums both outputs to provide the QAM signal.
Using the MAX5181/MAX5184 for Arbitrary Waveform Generation
Designing a traditional arbitrary waveform generator (AWG) requires five major functional blocks (Figure 8a): clock generator, counter, waveform memory, DAC for waveform reconstruction, and output filter. The waveform memory contains the sequentially stored digital replica of the desired analog waveforms. This memory shares a common clock with the DAC.
12
For each clock cycle, a counter adds one count to the address for the waveform memory. The memory then loads the next value to the DAC, which generates an analog output voltage corresponding to that data value. A DAC output filter can either be a simple or complex lowpass filter, depending on the AWG requirements for waveform function and frequencies. The main limitations of the AWG's flexibility are DAC resolution and dynamic performance, memory length, clock frequency, and the filter characteristics. Although the MAX5181/MAX5184 offer high-frequency operation and excellent dynamics, they are suitable for relaxed requirements in resolution (10-bit AWGs). To increase an AWG's high-frequency accuracy, tempera-
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10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
+3V + +3V + 10F 0.1F AVDD CLK DVDD CREF OUTP 10F 0.1F
AVDD
0.1F 402 402 +5V OUTPUT 400*
D0-D9
MAX5181 MAX5184
REFO 0.1F 400* OUTN
402
-5V 402
MAX4108
REFR RSET** DGND REN AGND
**MAX5181 ONLY
*400 RESISTORS INTERNAL TO MAX5184 ONLY.
Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier
+3V
AVDD
DVDD +3V
I COMPONENT 10 MAX5181 MAX5184
BP FILTER
DIGITAL SIGNAL PROCESSOR
AVDD
DVDD
CARRIER FREQUENCY
0 90
IF
Q COMPONENT 10 MAX5181 MAX5184
BP FILTER
MAX2452
QUADRATURE MODULATOR
Figure 7. Using the MAX5181/MAX5184 for I/Q Signal Reconstruction
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10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
AVDD
DVDD
LOWPASS RECONSTRUCTION FILTER
COUNTER CLOCK GENERATOR
ADR
WAVEFORM MEMORY (RAM)
DATA 10
MAX5181 MAX5184
400* VARIABLE fc
FILTERED WAVEFORM (ANALOG OUTPUT)
9.6k*
*MAX5181 ONLY
Figure 8a. Traditional Arbitrary Waveform Generation
CLOCK GENERATOR AVDD A D D E R DVDD LOWPASS RECONSTRUCTION FILTER
PIR
PHASE ACCUMULATOR
ADR
WAVEFORM MEMORY (RAM)
DATA 10
PHASE INCREMENT REGISTER
MAX5181 MAX5184
ACCUMULATOR FEEDBACK LOOP FOR DATA BITS 400* 9.6k* VARIABLE fc
FILTERED WAVEFORM (ANALOG OUTPUT)
*MAX5181 ONLY
Figure 8b. Direct Digital Synthesis AWG
ture stability, wide-band tuning, and past phase-continuos frequency switching, the user may approach a direct digital synthesis (DDS) AWG (Figure 8b). This DDS loop supports standard waveforms that are repetitive, such as sine, square, TTL, and triangular waveforms. DDS allows for precise control of the data-stream input to the DAC. Data for one complete output waveform cycle is sequentially stored in a RAM. As the RAM addresses are changing, the DAC converts the incoming data bits into a corresponding voltage waveform. The resulting output signal frequency is proportional to the frequency rate at which the RAM addresses are changed.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the MAX5181/MAX5184's performance. Unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections, which may affect dynamic specifications like SNR or SFDR. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5181/ MAX5184. Therefore, grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. First, a multilayer PC board with separate ground and power-supply planes is recommended. High-speed signals should be run on controlled impedance lines
14
______________________________________________________________________________________
10-Bit, 40MHz, Current/Voltage-Output DACs
directly above the ground plane. Since the MAX5181/ MAX5184 have separate analog and digital ground buses (AGND and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two. Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. Both devices have two power-supply inputs: analog VDD (AVDD) and digital VDD (DVDD). Each AVDD input should be decoupled with parallel 10F and 0.1F ceramic-chip capacitors. These capacitors should be as close to the pin as possible, and their opposite ends should be as close as possible to the ground plane. The DVDD pins should also have separate 10F and 0.1F capacitors adjacent to their respective pins. Try to minimize analog load capacitance for proper operation. For best performance, bypass with low-ESR 0.1F capacitors to AVDD. The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi network can also improve performance.
MAX5181/MAX5184
Pin Configurations (continued)
TOP VIEW
OUTN OUTP
DGND
Chip Information
SUBSTRATE CONNECTED TO AGND
REFO
CREF
REFR
24
23
22
21
20
+
AGND AVDD DACEN PD CS CLK 1 2 3 4 5 6
19
Package Information
18 17 16 DVDD D9 D8 D7 D6 D5
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 24 QSOP 24 TQFN PACKAGE CODE E24+1 T2444+4 OUTLINE NO. 21-0055 21-0139 LAND PATTERN NO 90-0172 90-0222
MAX5184
15 14 EP 13
10
11 D3
D1
REN
D0
TQFN-EP
______________________________________________________________________________________
D2
D4
12
7
8
9
15
10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184
Revision History
REVISION NUMBER 4 5 REVISION DATE 4/03 8/10 -- Added lead-free and automotive qualified parts to Ordering Information DESCRIPTION PAGES CHANGED -- 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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